In view of the lightweight, meticulous and multi-functional requirements of the mobile devices and the Internet of Things (IoT) products in the future, functional integration of key components of related integrated circuit (IC) functions is increased. The quantity of the Input/Output (I/O) in a wafer increases significantly with the refinement of the chip process line, and the traditional bridge IC/PCB packaging integration technology has not been used enough. The wafer package structure of high resolution, low cost and low stress will be the industry demand.
The reliability of the wafer package structure has been an important issue for the overall performance of the wafer. When the density distribution of the Input/Output metal pad is getting higher and higher in the recent packaging process, the stress easily focuses around the conductive bumps. When the wafer package structure is bent, the stress will focus on the corner of the conductive bump. The wafer package structure will be broken and the reliability will fail. In addition, during the removal process of the wafer package module, it is also easy to increase the risk of delamination of the package structure due to the stress being over concentrated on the conductive bumps.
Accordingly, how to solve the existing stress uneven distribution leading poor reliability of the chip package structure is the current issue.